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Exploration plays an important role in the design of high-performance pipelines. We propose an exploration strategy for varying three design parameters by using a performance-constrained component selection and pipelining algorithm on different ``architectures''. The architecture is specified manually by using a mix of behavioral and structural constructs, while the component selection and pipelining is performed automatically using our algorithms. Results on two industrial-strength DSP systems, indicate the effectiveness of our strategy in exploring a large design space within a matter of seconds.

As methodologies and tools for chip-level design mature, design effort becomes focused on increasingly higher levels of abstraction. We present a methodology and tool for system-level specification, design and refinement that result in an executable specification for each system component. The specification for each component can then be synthesized into hardware or compiled to software. We highlight advantages of the proposed methodology compared to current practice.

Given a set of communication channels to be implemented as a single bus, we present a bus-generation algorithm which determines the width of a bus implementation. Tradeoffs between the width of the bus and the performance of the processes communicating over the bus are evaluated. The algorithm incorporates system level constraints such as data transfer rates and the number of pins and allows several channels that may be transferring different sizes of data to be implemented as a single bus. We demonstrate through a detailed example the usefulness of the algorithm in implementing system-level interfaces between modules.

As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. In this paper, issues related to the specification of embedded systems are discussed. We compare VHDL with five other specification languages: HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system-level are highlighted. We conclude by presenting a list of features which are desirable in a language to be used for specifying systems.

Behavioral partitioning can be applied to attain various goals, one of which is the satisfaction of chip-packaging constraints. Such partitioning heavily influences decisions made in subsequent structural design, and may therefore lead to higher performance designs and more efficient use of area and pins than possible when structure is designed before partitioning. Current behavioral partitioning approaches are limited in that they partition at the level of control/dataflow graph operations. We introduce a new approach which partitions entire computations of a behavioral specification, such as processes and procedures, into chip behavioral specifications. We demonstrate the approach's usefulness and highlight results of several examples.

High-level synthesis tools often use parameterized component generators for describing the synthesized RT design. Rapid area and delay estimation of the instantiated components is necessary for effective component selection and allocation, and is crucial for performing design space exploration. Although constructive methods yield good estimates, they require excessive run times and thus have to be run off-line. In this paper, we describe a fast (on-line) method for estimating the area and delay of regular-structured generic RT components that are tuned to a particular technology library. The estimation models are generated using a least-square approximation on a set of sample data points from selected component implementations. Our approach has been tested against real data points on combinational as well as sequential components and the results show a prediction of the area and delay to within 10% of the actual values. These models have also been integrated with a high-level synthesis system to permit on-line estimation of a component's area and delay.

There is a need for capturing behavioral specifications of entire systems and obtaining multi-chip designs from those specifications. We discuss system level specification and synthesis issues, along with the unique requirements they place on a specification language. Since no current language meets those requirements, the SpecCharts language was created on top of VHDL. Its model and constructs permit capturing system specifications simply and precisely, while aiding synthesis.

Languages based on hierarchical and concurrent state diagrams are powerful in specifying system level designs. Simulating such languages can be simplified by translating to a simulation language such as VHDL and then using available simulators. This paper describes system level abstractions commonly found in specification languages and presents semantic preserving VHDL implementations.