Journal Articles

Weisheng Duan, Falko Kuester, Jean-Luc Gaudiot, and Omar Hammami, “Automatic Object and Image Alignment using Fourier Descriptors,” to appear in Image and Vision Computing, in press (2008).

T. Givargis, F. Vahid, and J. Henkel, “System-Level Exploration for Pareto-Optimal Configurations in Parameterized System-on-Chip,” IEEE/ACM Digest of Technical Papers for the International Conference on Computer Aided Design (ICCAD 2001), November 4-8, 2001, pp 25-30.

D. Shin, A. Gerstlauer, R. Doemer, D. Gajski, “An Interactive Design Environment for C-based High-level Synthesis of RTL Processors,” IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 4, pp. 466-475, April 2008.

P. Heydari and R. Mohanavelu, “Design of Ultra High-Speed Low-Voltage CMOS CML buffers and Latches,” to appear in IEEE Trans. on VLSI Systems, 2004.
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P. Heydari and M. Pedram, “Ground Bounce in Digital VLSI Circuits,” IEEE Trans. on VLSI Systems, Vol. 11, No. 2, pp 180-193, April 2003.
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J. Zhu, D. D. Gajski, ” An Ultra-Fast Instruction Set Simulator,” IEEE Transactions on VLSI, Vol. 10, No. 3, June 2002, pp 363-373

S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, “FABSYN: Floorplan-aware Bus Architecture Synthesis,” IEEE Trans. on VLSI, Vol 14, No. 3, March 2006, pp 241-253.
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Farhan Simjee and Pai H. Chou, “Efficient Charging of Supercapacitors for Extended Lifetime of Wireless Sensor Nodes,” in IEEE Transactions on Power Electronics, Volume 23, Issue 3, May 2008. pages 1526–1536.

T. Nakano and T. Suda, “Self-Organizing Network Services with Evolutionary Adaptation,” IEEE Transactions on Neural Networks, Special Issue on Adaptive Learning Systems in Communication Networks, Vol. 16, No. 5 September 2005.
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P. Chandraiah, R. Doemer: “Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 1078-1090, June 2008.

S. Pasricha, N. Dutt, M. Ben-Romdhane, “BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), vol.26, no.8, pp.1454-1464, August 2007.

E. Bozorgzadeh, S. Ghiasi, and M. Sarrafzadeh, “Optimal Integer Delay Budget Assignment on Directed Acyclic Graphs,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,Vol. 23, No. 8, pp 1184- 1199 , August 2004.
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E. Bozorgzadeh, R. Kastner, and Majid Sarrafzadeh, “Creating and Exploiting Flexibility in Rectilinear Steiner Trees,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 605-615, Vol. 22, No. 5, May 2003.
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Q. Zhang and I. G. Harris, “Partial BIST Insertion to Eliminate Data Correlation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 3, March 2003.
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T. Givargis and F. Vahid, “Platune: A Tuning Framework for System-on-Chip Platforms,” IEEE Transactions on Computter-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 11, November 2002, pp 1317-1327.

I. G. Harris and R. Tessier, “Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 21, No. 11, November 2002.
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R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 777-790, vol. 21, No. 7, July 2002.
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I. Bayraktaroglu and A. Orailoglu, “Concurrent Test for Digital Linear Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 9, September 2001, pp 1132-1142.

Jung-Yup Kang, Sandeep Gupta, and Jean-Luc Gaudiot, “An Efficient Data-Distribution Mechanism in a PIM (Processor-In-Memory) Architecture Applied to Motion Estimation,” IEEE Transactions on Computers, Vol. 57, No. 3, March 2008.

P. Biswas , and N. Dutt, “Code Size Reduction in Heterogeneous-Connectivity-based DSPs using Instruction Set Extensions,” IEEE Transactions on Computers , Vol 54, No. 10, October 2005, pp. 1216-1226.
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P.D’Alberto, A.Nicolau, A. Veidenbaum, and R.Gupta, “Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache,” 
IEEE Transactions on Computers, February 2005.
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A. Gordon-Ross and F. Vahid, “Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware,” IEEE Transactions on Computers, Special Issue-Embedded Systems, Microarchitecture, and Compilation Techniques , October 2005, Vol. 54, Issue 10, pp 1203-1215.
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P. Heydari , “Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise,” To appear in IEEE Trans. on Circuits and Systems I , 2004.
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P. Heydari, S. Abbaspour, and M. Pedram, “Interconnect Energy Dissipation in High-Speed ULSI Circuits,” to appear in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, 2004.
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J. Suzuki and T. Suda, “A Middleware Platform for a Biologically-inspired Newtork Architecture Supporting Autonomous and Adaptive Applications,” IEEE Journal on Selected Areas in Communications, Special issue on Intelligent Services and Applications in Next Generation Networks, Vol. 23, No. 2, February, 2005.

K. Fujii and T. Suda , “Semantics-based Dynamic Service Composition,” IEEE Journal on Selected Areas in Communications, Special Issue on Autonomic Communication Systems,Vol. 23, No. 12, December 2005.
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Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, and Daniel Gajski, “Automatic TLM Generation for Early Validation of Multicore Systems,” pp 10-19, Vol. 28, No. 3, May-June 2011.
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Weiwei Chen, Xu Han, and Rainer Doemer, “Multicore Simulation of Transaction-Level Models using the SoC Environment,” pp 20-31, Vol. 28, No. 3, May-June 2011.
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C.Park, J. Liu, and P. Chou, “B#: a Battery Emulator and Power Profiling Instrument,”
pp 150-159, March-April, 2005.

S. Pasricha, M. Luthra, S. Mohapatra, N. Dutt, N. Venkatasubramanian, “Dynamic Backlight Adaptation for Low-Power Handheld Devices,” pp 398-405, September-October 2004.
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S. Ozev, I. Bayraktaroglu, and A. Orailoglu, “Seamless Test of Digital Components in Mixed-Signal Paths,” IEEE Design & Test of Computers, pp 44-55, January-February 2004.

I. G. Harris, “Fault Models and Test Generation for Hardware-Software Covalidation,” IEEE Design and Test of Computers, Vol. 20, No. 4, July-August 2003.
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