Conference Proceedings

Location: Las Vegas, NV
Web Site: http://www.world-academy-of-science.org/IMCSE2005/ws/MSV

T. Harmon and R. Klefstad, “VADRE: A Visual Approach to Performance Analysis of Distributed, Real-Time Systems,” International Conference on Modeling, Simulation, and Visualization Methods, June 27-30 2005.

Location: Vienna, Austria
Web Site: http://www.itsc2005.at/

Y. Zhang, M. Lai, R. Klefstad, R. Lavanya, R. Jayakrishnan, ” A Distributed, Scalable, and Synchronized Framework for Large-Scale Microscopic Traffic Simulation,” IEEE International COnference on Intelligent Transportation Systems, September 13-16, 2005.

Location: Atlanta, GA
Web Site: http://www.iccs-meeting.org/papers.htmz

J-Y Kang and J-L Gaudiot, “A Logarithmic Time Method for Two’s Complementation,” International Conference on Computational Science (ICCS 2005), May 22-25, 2005.download pdf

Location: Jersey City, NJ
Web Site: http://www.princeton.edu/~wolf/EMSOFT-2005/index.htm

G. Madl, S. Abdelwahed, “Model-based Analysis of Distributed Real-time Embedded System Composition,” EMSOFT, September 2005.download pdf

A. Kejariwal, A. Azevedo, A. Veidenbaum, and A. Nicolau, “High Performance Annotation-aware JVM for Java Cards,” EMSOFT, September 2005.

Web Site: http://www.nsti.org/Nanotech2005/

S. Hiyama, Y. Moritani, T. Suda, R. Egashira, A. Enomoto, M. Moore, and T. Nakano, “Molecular Communication,” NSTI Nanotech, May 8-12, 2005.

Location: San Francisco, CA
Web Site: http://www.casesconference.org/cases2005/

H. Oh, N. Dutt, S. Ha, “Single Appearance Schedule with Dynamic Loop Count for the Minimum Data Buffer from Synchronous Dataflow Graphs,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf

M. Ghodrat,T. Givargis, A. Nicolau, “Equivalence Checking of Arithmetic Expressions Using Fast Evaluation,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf

A. Shrivastava, I. Issenin, N. Dutt, “Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf

Location: Chicago IL
Web Site: http://www.sigda.org/glsvlsi/local2.html

A. Gordon-Ross, F. Vahid, N. Dutt, ” A First Look at the Interplay of Code Reordering and Configurable Caches,” Great Lakes Symposium on VLSI (GLSVLSI), April 2005.download pdf

Location: Jersey City, NY
Web Site: http://www.codes-isss.org/

M. Reshadi, D. Gajski, “A Cycle-Accurate Compilation Algorithm for Custom Pipelined Datapaths,” International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005.download pdf

A. Shrivastava, E. Earlie, N. Dutt, and A. Nicolau, “Aggregating Processor Free Time for Energy Reduction,” International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005.download pdf

D. Shin, A. Gerstlauer, R. Dömer, and D. Gajski, “Automatic Network Generation for System-on-Chip Communication Design,” International Conference on Hardware/Software Codesign and System Synthesis, September 2005.download pdf

Location: Portland, OR
Web Site: http://www.chi2005.org/

S. Cotterell and F. Vahid, “A Logic Block Enabling Logic Configuration by Non-Experts in Sensor Networks,” Conference on Human Factors in Computing (CHI), April 2005.download pdf

Location: San Jose, CA
Web Site: http://www.iccd-conference.org/

M. Reshadi, B. Gorjiara, D. Gajski, “Utilizing Horizontal and Vertical Parallelism with No-Instruction-Set Compiler for Custom Datapaths,” International Conference on Computer Design (ICCD), October 2005.download pdf

M. Ramirez, A. Cristal, A. Veidenbaum, L. Villa, M. Valero, “A New Pointer-based Instruction Queue and Its Power-Performance Evaluation,” International Conference on Computer Design (ICCD 2005), October 2005. Best Paper Award at ICCD 2005