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Conference Proceedings

Symposium on Parallel Computing with FPGA’s (ParaFPGA)

Location: Juelich, Germany

Alex Nicolau, Furlong, J., A. Felch, J. Nageswaran, N. Dutt, A. Veidenbaum, A. Chandrashekar, and R. Granger,  “A Brain Derived Vision System Accelerated by FPGAs,” Proc. ParaFPGA: Parallel Computing with FPGA’s, September 4-7, 2007.

J. Furlong, A. Felch, J. Moorkanikara, N. Dutt, A. Nicolau, A. Veidenbaum, A. Chandrashekar, R. Granger, “Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements,” Proceedings of the 2007 Symposium on Parallel Computing with FPGA’s (ParaFPGA), Juelich, Germany, September 2007.

International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS)

Date: Sept. 30 – Oct. 5, 2007
Location: Salzburg, Austria
Website: http://www.ida.liu.se/cnferences/codes

G. Stitt and F. Vahid, “Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 2007, pp. 93-98

P. Chandraiah, R. Dömer: “Pointer Re-coding for Creating Definitive MPSoC Models”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2007: pp. 33-38

International Conference on Hardware/Software Codesign and System Synthesis

Location: Seoul, Korea
Website: http://www.ida.liu.se/conferences/codes/2006/

D. Shin, A. Gerstlauer, J. Peng, R. Dömer, D. Gajski, “Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration”, CODES+ISSS 2006, October 2006.
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G. Schirner, R. Dömer, “Accurate yet Fast Modeling of Real-Time Communication”, CODES+ISSS 2006, October 2006.
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Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian, “Design Space Exploration of Real-time Multi-media MPSoCs with Heterogeneous Scheduling Policies”, CODES+ISSS 2006, October 2006.

Design, Automation, and Test in Europe (DATE 2006)

Location: Munich, Germany
Website: http://www.date-conference.com/

P. Biswas and N. Dutt, “Automatic Identification of Application-Specific Funtional Units with Architecturally Visible Storage,” DATE ’06, March 2006.download pdf

R. Cornea, A. Nicolau, N. Dutt, ” Software Annotations for Power Optimization on Mobile Devices,” DATE ’06, March 2006.download pdf

S. Pasricha and N. Dutt, “COSMECA: Application Specific Co-Syntesis of Memory and Communication Architectures fo MPSoC,” DATE ’06, March 2006.download pdf

G. Schirner and R. Doemer, “Quantitative Analysis of Transaction Level Models for the AMBA Bus,” DATE ’06, March 2006.download pdf

S. Park, A. Shrivastava, N. Dutt, E. Earlie, A. Nicolau, Y. Paek, ” Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processesors,” DATE ’06, March 2006.download pdf

Asia South Pacific Design Automation Conference 2006 (ASP-DAC 2006)

Location: Yokohama, Japan
Web Site: http://www.aspdac.com/

B. Gorjiara, M. Reshadi, D. Gajski, “Designing a Custom Architecture for DCT Using NISC Design Flow,” ASP-DAC’06 Design Contest, January 2006.download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Constraint-Driven Bus Matrix Synthesis for MPSoC,” ASP-DAC’06, January 2006.download pdf

S. Banerjee, E Bozorgzadeh, N. Dutt, ” PARLGRAN: Parallelism Granularity Selection for Scheduling task chains on dynamically reconfigurable architectures,” ASP-DAC’06, January 2006.download pdf

H. Oh, N. Dutt, S. Ha, ” Memory Optimal Single Appearance Schedule wiht Dynamic Loop Count for Synchronous Dataflow Graphs,” ASP-DAC’06, January 2006.download pdf

H. Cho, S. Abdi, D. Gajski, “1D-19: Design and Implementation of a Duplex AMBA-TMS Transducer,” ASP-DAC’06, January 2006.download pdf