Conference Proceedings
Symposium on Parallel Computing with FPGA’s (ParaFPGA)
Location: Juelich, Germany
Alex Nicolau, Furlong, J., A. Felch, J. Nageswaran, N. Dutt, A. Veidenbaum, A. Chandrashekar, and R. Granger, “A Brain Derived Vision System Accelerated by FPGAs,” Proc. ParaFPGA: Parallel Computing with FPGA’s, September 4-7, 2007.
J. Furlong, A. Felch, J. Moorkanikara, N. Dutt, A. Nicolau, A. Veidenbaum, A. Chandrashekar, R. Granger, “Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements,” Proceedings of the 2007 Symposium on Parallel Computing with FPGA’s (ParaFPGA), Juelich, Germany, September 2007.
International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS)
Date: Sept. 30 – Oct. 5, 2007
Location: Salzburg, Austria
Website: http://www.ida.liu.se/cnferences/codes
G. Stitt and F. Vahid, “Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 2007, pp. 93-98
P. Chandraiah, R. Dömer: “Pointer Re-coding for Creating Definitive MPSoC Models”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2007: pp. 33-38
ACM SIGPLAN Principles and Practice of Parallel Computing (PPOPP 2007)
Location: San Jose, CA
Website: http://ftg.lbl.gov/ppopp07/
Alex Nicolau, Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos, “Tight analysis of the performance potential of thread speculation using spec CPU 2006”, Proc. PPOPP 2007: 215-225, June 2007.
21st ACM International Conference on Supercomputing (ICS 2007)
Location: Seattle, WA
Website: http://ics07.ac.upc.edu/
Alex Nicolau, P.D’Alberto, “Adaptive Strassen’s Matrix Multiplication”, Proc. ACM 21st International Conference on Supercomputing, June 2007.
IEEE International Parallel & Distributed Processing Symposium (IPDPS 2007), March 26-30, 2007
Location: Long Beach, California
Website: http://www.ipdps.org/
Kyueun Yi and Jean-Luc Gaudiot, “Architectural Support for Network Applications on Simultaneous MultiThreading Processors”
Akira Hatanaka , Nader Bagherzadeh, “A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template”
International Conference on Information Technology : New Generations (ITNG 2007) – April 2007
Location: Las Vegas, Nevada, USA
Website: http://www.itng.info/
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh, “Design and Analysis of a Feasible Network-on-Chip(NoC) Architecture”
Design Automation Conference (DAC 2007) – June 4-8 2007
Location: San Diego, USA.
Website: http://www.dac.com
Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan, “Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation”
International Symposium on Field-Programmable Gate Arrays (FPGA) – February 2007
Location: Monterey, California
Website: http://conferences.ece.ubc.ca/isfpga2007/main_intro.html
B. Gorjiara, D. Gajski, “FPGA-friendly Code Compression Technique for Statically Scheduled Horizontal Microcoded Custom IPs”
IEEE International High-Level Design
Yu, L. & Abdi, S., “Automatic TLM Generation for C-Based MPSoC Design,” Proceedings of the 2007 IEEE International High-Level Design, Validation and Test Workshop, November 2007.
International Embedded Systems Symposium (IESS 2007) – June 2007
Location: Irvine, California, USA
Website: http://www.iess.org/
Ilya Issenin, Nikil Dutt, “Data Reuse Driven Memory and Network-on-Chip Co-Synthesis”
J. Trajkovic, D. Gajski, “Automatic Data Path Generation from C code for Custom Processors”