Conference Proceedings

Location: Anaheim, CA
Website: http://www.nanoarch.org/08/index.html

S. Pasricha, N. Dutt, and F. Kurdahi. “System Level Performance Analysis of Carbon Nanotube Global Interconnects for Emerging Chip Multiprocessors,” Proceedings of  the IEEE/ACM International Symposium on NanoScale Architectures (NanoArch 2008), Anaheim, CA, June 2008.

Location: Anaheim, CA, United States
Website: http://www.dac.com/

N. Dutt, “ESL Hand-off: Fact or EDA Fiction?” Panel Position Statement, Proceedings of the Design Automation Conference 2008 (DAC 2008), Anaheim, CA, June 2008.

Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, and Alexander V. Veidenbaum, “Dynamic Register File Resizing and Frequency Scaling to Improve Embedded Processor Performance and Energy-Delay Efficiency,” Proc. of the Design Automation Conference (DAC) 2008.

Location: Anaheim, CA
Website: http://www.sasp-conference.org/

J. Trajkovic, D. Gajski, “Custom Processor Core Construction from C Code,” In Proceedings of Sixth IEEE Symposium on Application Specific Processors (June 2008).

Location: Las Vegas, Nevada, USA
Website: http://www.itng.info/

Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh, “Design and Analysis of a Feasible Network-on-Chip(NoC) Architecture”

Location: San Diego, USA.
Website: http://www.dac.com

Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan, “Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation”

Location: Monterey, California
Website: http://conferences.ece.ubc.ca/isfpga2007/main_intro.html

B. Gorjiara, D. Gajski, “FPGA-friendly Code Compression Technique for Statically Scheduled Horizontal Microcoded Custom IPs”

Yu, L. & Abdi, S., “Automatic TLM Generation for C-Based MPSoC Design,” Proceedings of the 2007 IEEE International High-Level Design, Validation and Test Workshop, November 2007.

Location: Irvine, California, USA
Website: http://www.iess.org/

Ilya Issenin, Nikil Dutt, “Data Reuse Driven Memory and Network-on-Chip Co-Synthesis”

J. Trajkovic, D. Gajski, “Automatic Data Path Generation from C code for Custom Processors”

Deyi Pi, Byung-Kwan Chun, and Payam Heydari, “A 2.5-3.2GHz Continuously-Tuned Varactor-Less LC-VCO,” IEEE Asian Solid-State Circuits Conference (A-SSCS), Nov. 2007.

Location: Paphos, Cyprus.
Website: http://www.liacs.nl/~marcello/FMOODS/index.htm

Minyoung Kim, Mark-Oliver Stehr, Carolyn Talcott, Nikil Dutt, Nalini Venkatasubramanian, “A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems”, LNCS 4468 pages 285-300