D. D. Gajski, L. Cai, “Variable Mapping of System Level Design," TR 02-32, October 8, 2002. download pdf
D. Shin, D. D. Gajski, “Scheduling in RTL Design Methodology,” TR 02-11, April 12, 2002. download pdf
D. D. Gajski, L. Cai, “Grouping-Based Architecture Exploration of System-Level Design," TR 02-31, August 16, 2002. download pdf
T. Givargis, “Optimal Indexing for Cache Miss Reduction in Embedded Systems,” TR 02-10, July 4, 2002. download pdf
S. Gupta, N. Savoiu, N. Dutt, R. Gupta, A. Nicolau, “Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis," TR 02-29, October 1, 2002. download pdf