Elaheh Bozorgzadeh

Contact Information

Design Automation and Synthesis for Embedded Systems
eli@ics.uci.edu
(949) 824-8860
https://eli.ics.uci.edu/

Professor Bozorgzadeh’s Research

Research Interests

• System Synthesis for Self-adaptive Reconfigurable Embedded Systems
• Energy Sustainability in Embedded systems through micro energy harvesting
• Physically-aware Architectural Synthesis and layout planning for Embedded Systems
• FPGA-Based Accelerated Computing

Awards

• NSF CAREER Award, 2008
• Best paper award, IEEE International Conference in Field Programmable Logic and Applications (FPL), 2006.

Past Projects

Predictable Design by Timing Budget Management

In order to abstract away the design complexity, each design is decomposed into a set of sub-designs and hierarchical design process is applied. Along with this hierarchical planning and the passing of the design through discrete independent stages, there lie serious issues in design convergence. Along with timing, there are other constraints such as size, power dissipation, etc. The sub-designs along the critical paths are the most constrained components during the optimization process in CAD flow. However, timing constraint is more relaxed on the other parts of the design. This excess delay (or relaxation) referred to as delay budget
can be exploited for further optimization on other design objectives. Timing budget management assign timing constraints (or upper bound) on each sub-design. Delay Assignment is applied at all behavioral levels of abstraction in VLSI CAD flow. The main theme of this project is investigation of early management of delay constraints and prediction of design quality to ensure design convergence. We propose and analyze problems on delay budgeting while considering incremental features and predictability in design flow. The optimization problems we currently aim at (but not limited to) are maximum delay budgeting, probabilistic/statistical delay budgeting, incremental delay budgeting and time criticality management.

Dynamic Hardware Reconfiguration and Reconfigurable Computing 

There are various strong reasons motivating the integration of programmability and reconfigurability in system design. The increasing number of applications and shorter time-to-market enhances the need for design re-use which can be realized efficiently by reconfigurability in the system. However, hardware reconfiguration comes with the cost of degradation in performance, area and, power. However, the methodologies for reconfiguration have a key role in management of this drawback. This project focuses on exploitation of hardware reconfigurability in reconfigurable system-on-chip. The research plan is concentrated on both aspects of development of task-level compilation flow and architectural exploration for efficient reconfiguration support. The design tasks we are currently focusing are on are hw/sw partitioning with dynamic reconfiguration, task scheduling and resource management.

Heterogeneous FPGA Architecture and Supportive CAD Design

Heterogeneity in FPGA architecture design is growing both in routing architecture and logic blocks. In this project, we aim at developing new CAD tools to support FPGA devices with embedded IPs such as multipliers, memory blocks, and processors. Along with it, we research on multi-segmentation in routing architecture and exploring new heterogeneity factors in routing architecture. The latter problem is a joint research project with Prof. Kia Bazaragn (Univ. of Minnesota) and Prof Ryan Kastner (UCSB) and their students.

Another project is on connectivity between the embedded cores and reconfigurable fabric on FPGA devices. Example of cores are embedded multiplier, memories, processors, or other application specific units. Simin Dai has started working on this project.

For more information, please visit Professor Bozorgzadeh’s website.