Daniel D. Gajski

Contact Information

Office: 3221 Engineering Hall
Lab: 2008 Anteater Instruction & Research Building
Email: gajski@uci.edu
Phone: (949) 824-4155 Office
https://www.cecs.uci.edu/~gajski/

Professor Gajski’s Research

Research Interests

Daniel Gajski is particularly interested in requirements and specifications of embedded systems and the design process that leads from an executable specification to the final manufacturable blueprint. In order to study the design process, his group is developing new specification languages and modeling guidelines, as well as simulation, synthesis, and verification tools. In order to obtain efficient specifications and design models, they are taxonomizing models of computations, platform architectures and design styles. In order to develop efficient CAD tools, they are studying synthesis algorithms for systems, architectures, processors, controllers, datapaths, and other intellectual properties (IPs). Their further goal is to build proof-of-concept tools and prove our methodology for different application domains and tools on extensive industrial-strength examples.

Embedded Systems Methodology Group

Our main focus is currently on developing new algorithms, tools, and design flows in the context of a comprehensive SoC system-level design methodology. The results of these research efforts will flow into building different tool sets that are part of the envisioned SoC design flow.

System-on-Chip Design Environment (SCE) 

                          

Web Site: https://www.cecs.uci.edu/~cad/sceMain.html

SCE is an Interactive environment for system-level design that starts from an executable specification and ends with a cycle-accurate model of the system that composes of a variety of processors, IPs, memories and buses executing the specification in a distributed fashion. SCE allows designers to make all decisions such as selecting and connecting components, partitioning computations and communications, scheduling, etc. While SCE performs automatic transaction level model generation, simulation, verification, and exploration.

Verification Through Model Algebra

This project defines levels of abstractions in modeling systems and rules for transformation between them in the form of a model algebra. Such well-defined models and sequence of transformation between them allow verification of model equivalence which is not possible for too independently generated models of the same design.

NISC: No-Instruction-Set-Computer 

NISC Demo: https://www.cecs.uci.edu/~nisc/ 

NISC projects unites HW and SW views of computation by defining the model that unties traditional concepts of custom HW (RTL and NISC processors) with concepts of standard processors (RISC and CISC processors).