Contact Information

Parallel Computation, Architectures, Compilers, Programming Languages
anicolau@uci.edu
(949) 824-4079
https://faculty.uci.edu/profile/?facultyId=2080
http://www.ics.uci.edu/~nicolau/

Professor Nicolau’s Research

Research Interests

Parallel programs, especially those with truly critical time (speed) requirements, are difficult to design. The process is extremely error-prone, tedious and time-consuming. The first goal of Dr. Nicolau’s work is to design and implement a system of program transformations that support the semi-automatic (and eventually fully-automatic) exploitation of substantially all the parallelism available in a given program.

Parallelizing Compilers, High-Performance Java, Power-aware Computing, Reconfigurable Computing.

Current Projects

• Julius C: Compiler Optimizations for Divide and Conquer ApplicationsJulius C is a C compiler that determines a model for divide and conquer algorithms. The model is an extension of the call graph and it conceives information about the dynamic behavior of the algorithm. The use of the model is twofold: at compile time, the model drives code generation and code optimizations; at run time, the model offers a support driving code execution, code adaptation and hardware adaptation.
• EXPRESS Retargetable CompilerEXPRESS is an optimizing, memory-aware, Instruction Level Parallelizing (ILP) compiler. EXPRESS uses the EXPRESSION ADL to retarget itself to a wide class of processor architectures and memory systems. The inputs to EXPRESS are the application specified in C, and the processor architecture specified in EXPRESSION. The front-end is GCC-based and performs some of conventional optimizations. The core transformations in EXPRESS include RDLP — a loop pipelining technique, TiPS : Trailblazing Percolation Scheduling — a speculative code motion technique, Instruction Selection, Register Allocation and If-Conversion — a technique for architectures with predicated Instruction Sets. The back-end generates assembly code for the processor ISA.
• FORGE: A Framework for Optimization of Distributed Embedded Systems SoftwareThe FORGE project is a framework for optimization of distributed embedded systems software, which integrates the middleware abstraction layer with the hardware/OS abstraction layer and studies mechanisms for capturing resources/architectures at these two levels and allowing interactions between the levels. A resource description language (RDL) specifying the composition of the system as well as resource constraints can be used by a compiler for automatically generating the necessary services and middleware configuration and their deployment across the platform.
• SPARK: High-Level Synthesis using Parallelizing Compiler TechniquesSPARK is a C-to-VHDL high-level synthesis framework that employs a set of innovative compiler, parallelizing compiler, and synthesis transformations to improve the quality of high-level synthesis results. The compiler transformations have been re-instrumented for synthesis by incorporating ideas of mutual exclusivity of operations, resource sharing and hardware cost models.
• CoReComp: A Compiler Framework for Mapping Applications on Mesh-Based Coarse-Grain Reconfigurable ArchitecturesCoarse-grain reconfigurable architectures trade-off some of the configuration flexibility of fine-grain FPGAs in return for smaller delay, area and configuration time. They provide massive parallelism, high computational capability and their behavior can be configured dynamically, thus making them a better alternative to ASICs and fine-grain FPGAs in many aspects. Mapping applications to such architectures is a complex task that is a combination of the traditional operation scheduling, operation to PE binding (or mapping), and routing problems. The focus of this research is to build a compiler framework which should be capable of mapping applications on reconfigurable architectures by taking into account different architecture and application parameters.