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ESE: Embedded System Environment

Release Date: March 28, 2008Web Site: https://www.cecs.uci.edu/~ese/ ESE is a toolset for modeling, synthesis and validation of multi-processor embedded system designs. It builds on over 15 years of research in system level design at CECS under Prof. Daniel Gajski. It consists of two parts: ESE Front End and ESE Back End. ESE Front End provides automatic generation of SystemC transaction […]

Hardware-Accelerated Formal Verification

by Prof. Masahiro FujitaVLSI Design and Education Center University of Tokyo, Tokyo, Japan McDonnell Douglas Auditorium, University of California, Irvine Distinguished Lecture, April 29, 2008 Abstract

NISC: No-Instruction-Set-Computer

Release Date: May 2008 (NISC Toolset 2008.05)NISC Demo: https://www.cecs.uci.edu/~nisc/  No-Instruction-Set-Computer (NISC) Technology is the next generation of tools for Design Synthesis. With NISC Technology, you can simultaneously gain higher productivity and better […]

CECS DAC Open House

The 45th Design Automation Conference (DAC) is being held in Anaheim, CA on June 8-13, 2008. CECS cordially invites DAC attendees to an Open House on Friday afternoon, June 13, 2008 from 2:00PM to 4:00PM in our CECS office on the 2rd floor of the Anteater Instruction & Research Building (AIRB). We are planning a […]