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Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow

Title:  “Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow” Speaker: Christian Krieg, Vienna University of Technology, Vienna, Austria Date and Time: Thursday, November 17, 2016 at 2:00 PM Location: Donald Bren Hall 3011 Host:  Professor Nikil Dutt Abstract: We present a novel type of Trojan trigger targeted at the field-programmable […]

Low Energy, a New Trend for Lightweight Cryptography

Title: “Low Energy, a New Trend for Lightweight Cryptography” Speaker: Dr. Francesco Regazzoni, ALaRI Institute of Università della Svizzera italiana, Lugano, Switzerland Date and Time:  Wednesday, February 1, 2017 at 11:00 a.m. Location: DBH 4011 Host: Prof. Nikil Dutt Abstract: In the last decade, several lightweight block ciphers and hash functions have been proposed. One […]

Resource Aggregation for Collaborative Projected Video from Multiple Mobile Devices

Name: Hung Nguyen Date: November 17, 2016 Time: 1:30 P.M. Location: EH 3206 Committee: Fadi Kurdahi (Chair), Aditi Majumder (Co-Chair) Abstract:  We explore and develop an embedded real time system and associated algorithms that enable an aggregation of limited resource, low-quality, projection-enabled mobile devices to collaboratively produce a higher quality video stream for a superior viewing […]

On Optimizing the Performance of Interference-Limited Wireless Systems

Name: Rana A. Abdelaal Date: January 30, 2017 Time: 1:00 PM Location: Engineering Hall 3106 Committee: Professor Ahmed Eltawil Abstract: Multi Input Multi Output (MIMO) technology has seen prolific use to achieve higher data rates and an improved communication experience for cellular systems. However, one of the challenging problems in MIMO systems is interference. Interference limits the […]

Runtime Memory Management in Many-core Systems

Name: Hossein Tajik Date: November 15, 2016 Time: 3:00PM - 4:00PM Location: DBH 3011 Conference Room Committee: Nikil Dutt (Chair), Tony Givargis, Alex Nicolau Abstract: With the increasing number of cores on a chip, we are moving towards an era where many-core platforms will soon be ubiquitous. Efficient use of tens to hundreds of cores on […]

Low Power Reliable Design using Pulsed Latch Circuits

Name: Wael Mahmoud Elsharkasy Date: February 15, 2017 Time: 11:00 AM Location: Engineering Hall 3206 Committee: Prof. Fadi J. Kurdahi, Prof. Ahmed Eltawil, Rainer Doemer Abstract: System-on-Chip (SoC) faced lots of challenges over the past decade. With nowadays applications centered around Internet-of-Everything (IoE), these challenges are expected to be more critical. Among these challenges are the reduction of power consumption […]

Optimizing Many-Threads-to-Many-Cores Mapping in Parallel Electronic System Level Simulation

Name: Guantao Liu Date: March 2, 2017 Time: 4:00 PM Location: Engineering Hall 3206 Committee: Rainer Doemer (Chair), Kwei-Jay Lin, Mohammad Al Faruque Abstract: In hardware/software co-design, Discrete Event Simulation (DES) has been in use for decades to verify and validate the functionality of Electronic System Level (ESL) models. Since the parallel computing platforms are readily available […]

Distinguished Lecture at CECS

Title:  "Processor Paradigms: Evolution or Disruption and the importance of the Transformation Hierarchy Moving Forward" Speaker: Prof. Yale N. Patt, University of Texas, Austin TX Date and Time: Friday, March […]

Heterogeneous Chip Architectures for Big Data Analytics

Title: "Heterogeneous Chip Architectures for Big Data Analytics" Speaker: Houman Homayoun, George Mason University, Virginia Date and Time: Friday, April 28, 2017 at 11:00AM Location: 2430 Engineering Hall Abstract: There is a fundamental shift underway now in various industry sectors to transport their big data to the clouds, thus increasing their efficiency and improving cash flow. In […]