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Latest Past Events

Pareto Exploration Methodology for Future Logic Technology Options in Domain-Specific Processors

EH 2430 Engineering Hall, University of California, Irvine, Irvine

Scaling of Si-CMOS based logic processor circuits is hitting limits on application-level performance (throughput and latency), dynamic and leakage power, and even cost characteristics. For that reason, several researchers have started to study alternatives based on so-called beyond CMOS devices.

“Capstone: A Capability-based Foundation for Trustless Secure Memory Access”

EH 2430 Engineering Hall, University of California, Irvine, Irvine

Speaker: Jason Zhijingcheng Yu Date and Time: Monday, August 7th, 11:00 am Location: EH 2430 Abstract: Capability-based memory isolation is a promising new architectural primitive. Software can access lowlevel memory only via […]