Nonlinear Symbolic Program Analysis for Increased Parallelization
Prof. Kleanthis Psarris, Department of Computer Science, University of Texas at San Antonio, TXMarch 9, 2009
949-824-9127
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Seminars at CECS
Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
Dr. Hiroshi Nakamura, University of Tokyo, JapanMay 4, 2009 (Lecture Cancelled)
Compiler-enabled Power-efficient Register File Protection
by Dr. Jongeun LeeEECS, Ulsan National Institute of Science and Technology,Korea
Donald Bren Hall (DBH) 3011 Date & Time
Seminar, July 22, 2009
Portable Direct Methanol Fuel Cell System for Green Computing
by Dr. Naehyuck ChangSeoul National University
CalIT2 Room 3008
Seminar, August 5, 2009
Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA
Prof. Lei He, Electrical Engineering Department, UCLAOctober 9. 2009
Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
Dr. Hiroshi Nakamura, University of Tokyo, JapanOctober 19, 2009
A Virtualization-Based Software Architecture for Real-Time Embedded Systems
Dr. Sung-Soo Lim, Kookmin University, KoreaOctober 22, 2009
NEC’s Manycore Platforms for Low-Power Embedded System
Naoki Nishi GM, NEC Central Research Labs, JapanNovember 12, 2009
Energy Efficient Computing
by Prof. Tajana Simunic RosingDepartment of CSE, UC San Diego
Engineering Hall (EH) 2430
Seminar, November 16, 2009
Advanced SoC Architectures for Multiple DRAMs (Enabled by 3D Die Stacking)
by Dr. Sungjoo YooPOSTECH
Donald Bren Hall (DBH) 3011
Seminar, November 17, 2009
Concurrency and Communication: Lessons from the SHIM Project
Dr. Stephen A. Edwards,Columbia University
Donald Bren Hall (DBH) 4011
Seminar, November 18, 2009
STP Engine, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture, Tool, and Real System Usecases
Dr. Masato Motomura, NEC Labs, JapanDecember 14, 2009