Pareto Exploration Methodology for Future Logic Technology Options in Domain-Specific Processors
EH 2430 Engineering Hall, University of California, Irvine, IrvineScaling of Si-CMOS based logic processor circuits is hitting limits on application-level performance (throughput and latency), dynamic and leakage power, and even cost characteristics. For that reason, several researchers have started to study alternatives based on so-called beyond CMOS devices.