Towards Finding the Optimization Potential of Fine-Grained Locks

Name:  Ahmad Nahian

Chair: Professor Brian Demsky

Date: November 30, 2023

Time:  9:30 AM

Location: ISEB 1010

Committee: Professor Rainer Doemer, Professor Quoc-Viet Dang

Title: Towards Finding the Optimization Potential of Fine-Grained Locks

Abstract: Fine-grained locking is an effective way of eliminating lock contention in multi-threaded applications. However, it is comparatively difficult and error prone to implement. To help programmers know the optimization potential of implementing fine-grained locking we have developed an approach that overcomes several shortcomings of prior approaches like record/replay. Our approach executes the existing implementation of the multi-threaded program with a custom thread scheduler that schedules threads according to their logical time, which is the time it would have taken to execute the thread without waiting for unnecessary lock contention. The custom thread scheduler leverages a prediction mechanism to predict conflict relations among critical sections so that it schedules threads to generate the execution of an implementation with optimal fine-grained locking. We have implemented our approach in FGLPerf and tested it on several multi-threaded benchmarks.

Short Bio: Ahmad Nahian is a PhD candidate in the EECS Computer Engineering program at UC Irvine, working under the supervision of Professor Brian Demsky. Ahmad Nahian attained his BS in Computer Science and Engineering from Bangladesh University of Engineering and Technology and MS in Computer Engineering from UC Irvine. A notable work of his research is information flow profiler that finds optimization opportunities in multi-threaded programs. The information flow profiler is a powerful tool in that it can find new optimization opportunities along with optimization insights to eliminate synchronization bottlenecks that cannot be discovered by other state of the art profilers.