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STP Engine, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture, Tool, and Real System Usecases
December 14, 2009 @ 3:00 pm - 4:00 pm PST
STP Engine, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture, Tool, and Real System Usecases
| Speaker | Dr. Masato Motomura, System IP Core Research Laboratories, NEC Corporation, Japan |
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| CECS Host | Professor Nikil Dutt | |||
| Location | Donald Bren Hall (DBH) 3011, University of California, Irvine | |||
| Date & Time | December 14, 2009 Refreshments at 1:30pm; Talk begins 2:00pm |
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| Abstract | Stream Transpose (STP) Engine is a programmable HW core to accelerate stream processing in modern system LSIs. It is composed of an array of numerous numbers of processing and memory elements as well as an intelligent data streaming HW mechanism. Key differentiation from other many-core type parallel architectures lies in its programming model: i.e., a design tool based on high-level HW synthesis technology compiles a C source code into a set of pseudo HW configurations which are spatially and temporally mapped onto the array. The STP engine is productized in 90nm-generation system LSIs, and is targeted for wider-range use in forthcoming generations beyond 40nm. | |||
| Biography | Dr. Motomura received EE doctorial degree from Kyoto University in 1996. He has been engaged in research of various LSI architectures, such as functional memories, parallel processors, and reconfigurable arrays in NEC research laboratories since 1987. From 2002 to 2009, he led technology and business development of STP Engine in NEC Electronics. He was also the winner of 1992 IEEE JSSC Best Paper Award. |