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FPGA 2001 :
[ <A HREF="fpgaabs.htm">Abstracts</A> ]
[ <A HREF="fpgasess.htm">Session Index</A> ]
[ <A HREF="fpgaai.htm">Author Index</A> ]</H3>
<HR>
<H2>FPGA 2001 Table of Contents</H2>
<B>
Sessions:
[<A HREF="#sess1">1</A>]
[<A HREF="#sess2">2</A>]
[<A HREF="#sess3">3</A>]
[<A HREF="#sess4">4</A>]
[<A HREF="#panel">Panel</A>]
[<A HREF="#sess5">5</A>]
[<A HREF="#sess6">6</A>]
[<A HREF="#sess7">7</A>]
[<A HREF="#sess8">8</A>]
[<A HREF="#posabs">Poster Paper</A>]
<P>
<A HREF="../../pdffiles/welcome.pdf">Welcome Message </A><BR>
<A HREF="../../pdffiles/pgm.pdf">Organizing Committee </A><BR>
<A HREF="../../pdffiles/pgm.pdf">Program Committee </A><P>
</B>
<HR>
<H2>Session 1: <A HREF="fpgaabs.htm#sess1" NAME="sess1">
Placement and Routing
</A></H2>
<I>Chair: Carl Ebeling, University of Washington</I>
<DL>
<DT>
<A HREF="fpgaabs.htm#1_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/1_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Timing-Driven Placement for Hierarchical Programmable Logic Devices [p. 3]
<DD><I>M. Hutton, K. Adibsamii, and A. Leaver (Altera Corporation)</I><P>
<DT>
<A HREF="fpgaabs.htm#1_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/1_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
LRoute: A Delay Minimal Router for Hierarchical CPLDs [p. 12]
<DD><I>
K. K. Lee (Synopsys, Inc.) and M. D. F. Wong (University of Texas at Austin)
</I><P>
<DT>
<A HREF="fpgaabs.htm#1_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/1_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Crosstalk-Aware Timing-Driven Router for FPGAs [p. 21]
<DD><I>S. J. E. Wilton (University of British Columbia)</I><P>
<DT>
<A HREF="fpgaabs.htm#1_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/1_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Runtime and Quality Tradeoffs in FPGA Placement and Routing [p. 29]
<DD><I>C. Mulpuri and S. Hauck (University of Washington)</I><P>
</DL>
<HR>
<H2>Session 2: <A HREF="fpgaabs.htm#sess2" NAME="sess2">
Technology Mapping
</A></H2>
<I>Chair: Steven Wilton, University of British Columbia</I>
<DL>
<DT>
<A HREF="fpgaabs.htm#2_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/2_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Performance-Driven Mapping for CPLD Architectures [p. 39]
<DD><I>D. Chen, J. Cong, M. D. Ercegovac, and Z. Huang (University of California, Los Angeles)</I><P>
<DT>
<A HREF="fpgaabs.htm#2_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/2_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Simultaneous Logic Decomposition with Technology Mapping in FPGA Designs [p. 48]
<DD><I>G. Chen and J. Cong (University of California, Los Angeles)</I><P>
</DL>
<HR>
<H2>Session 3: <A HREF="fpgaabs.htm#sess3" NAME="sess3">
Routing Architectures
</A></H2>
<I>Chair: Tom Kean, Algotronix</I>
<DL>
<DT>
<A HREF="fpgaabs.htm#3_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/3_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Using Sparse Crossbars within LUT Clusters [p. 59]
<DD><I>
G. Lemieux and D. Lewis (University of Toronto)
</I><P>
<DT>
<A HREF="fpgaabs.htm#3_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/3_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Detailed Routing Architectures for Embedded Programmable Logic IP Cores [p. 69]
<DD><I>
P. Hallschmid and S. J. E. Wilton (University of British Columbia)
</I><P>
<DT>
<A HREF="fpgaabs.htm#3_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/3_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Mixing Buffers and Pass Transistors in FPGA Routing Architectures [p. 75]
<DD><I>M. Sheng and J. Rose (University of Toronto)</I><P>
</DL>
<HR>
<H2>Session 4: <A HREF="fpgaabs.htm#sess4" NAME="sess4">
Applications
</A></H2>
<I>Chair: Ray Andraka, Andraka Consulting</I>
<DL>
<DT>
<A HREF="fpgaabs.htm#4_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/4_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Reprogrammable Network Packet Processing on the Field
Programmable Port Extender (FPX) [p. 87]
<DD><I>J. W. Lockwood, N. Naufel, J. S. Turner, and D. E. Taylor (Washington University)</I><P>
<DT>
<A HREF="fpgaabs.htm#4_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/4_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Fast Implementations of Secret-Key Block Ciphers Using
Mixed Inner- and Outer-Round Pipelining [p. 94]
<DD><I>P. Chodowiec, P. Khuon, and K. Gaj (George Mason University)</I><P>
<DT>
<A HREF="fpgaabs.htm#4_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/4_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Algorithmic Transformations in the Implementation of K-means
Clustering on Reconfigurable Hardware [p. 103]
<DD><I>M. Estlick, M. Leeser (Northeastern University), J. J. Szymanski,
and J. Theiler (Los Alamos National Laboratory)</I><P>
</DL>
<HR>
<H2>Panel: <A HREF="fpgaabs.htm#panel" NAME="panel">
Is Marriage in the Cards for Programmable Logic, Microprocessors and ASICs? [p. 111]
</A></H2>
<I>
Moderator: S. Kaptanoglu (Adaptive Silicon)<BR>
Panalists: J. East (Actel), T. Garverick (Adaptive Silicon), S. Hauck (University of Washington),
D. Papworth (Intel), D. Tavana (Triscend), S. Trimberger (Xilinx), and R. Vasishta (LSI Logic)
</I><P>
<DT>
<A HREF="fpgaabs.htm#panel"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/panel.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
</DL>
<HR>
<H2>Session 5: <A HREF="fpgaabs.htm#sess5" NAME="sess5">
Reconfigurable Computing
</A></H2>
<I>Chair: Steve Trimberger, Xilinx</I>
<DL>
<DT>
<A HREF="fpgaabs.htm#5_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/5_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Attacking the Semantic Gap Between Application Programming
Languages and Configurable Hardware [p. 115]
<DD><I>G. Snider, B. Shackleford, and R. J. Carter (Hewlett-Packard Laboratories)</I><P>
<DT>
<A HREF="fpgaabs.htm#5_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/5_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Matching and Searching Analysis for Parallel Hardware
Implementation on FPGAs [p. 125]
<DD><I>P. Moisset, P. Diniz, and J. Park (University of Southern California/Information Sciences Institute)
</I><P>
<DT>
<A HREF="fpgaabs.htm#5_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/5_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Evaluation of the Streams-C C-to-FPGA Compiler: An Applications Perspective [p. 134]
<DD><I>J. Frigo, M. Gokhale (Los Alamos National Laboratory), and D. Lavenier (IRISA-CNRS)
</I><P>
<DT>
<A HREF="fpgaabs.htm#5_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/5_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
The Effect of Reconfigurable Units in Superscalar Processors [p. 141]
<DD><I>J. E. Carrillo E. and P. Chow (University of Toronto)</I><P>
</DL>
<HR>
<H2>Session 6: <A HREF="fpgaabs.htm#sess6" NAME="sess6">
Pipelined Routing Architectures
</A></H2>
<I>Chair: Andre DeHon, Cal Tech</I>
<DL>
<DT>
<A HREF="fpgaabs.htm#6_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/6_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Interconnect Pipelining in a Throughput-Intensive FPGA Architecture [p. 153]
<DD><I>A. Singh, A. Mukherjee, and M. Marek-Sadowska (University of California, Santa Barbara)</I><P>
<DT>
<A HREF="fpgaabs.htm#6_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/6_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
The Case for Registered Routing Switches in Field Programmable Gate Arrays [p. 161]
<DD><I>D. P. Singh and S. D. Brown (University of Toronto)</I><P>
</DL>
<HR>
<H2>Session 7: <A HREF="fpgaabs.htm#sess7" NAME="sess7">
Issues in FPGA-Based Systems
</A></H2>
<I>Chair: Chuck Stroud, University of North Carolina-Charlotte</I>
<DL>
<DT>
<A HREF="fpgaabs.htm#7_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/7_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Configuration Compression for FPGA-based Embedded Systems [p. 173]
<DD><I>A. Dandalis and V. K. Prasanna (University of Southern California)</I><P>
<DT>
<A HREF="fpgaabs.htm#7_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/7_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Memory Coherence Technique for Online Transient Error
Recovery of FPGA Configurations [p. 183]
<DD><I>W.-J. Huang and E. J. McCluskey (Stanford University)</I><P>
<DT>
<A HREF="fpgaabs.htm#7_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/7_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Run-Time Defect Tolerance using JBits [p. 193]
<DD><I>P. Sundararajan and S. A. Guccione (Xilinx, Inc.) </I><P>
</DL>
<HR>
<H2>Session 8: <A HREF="fpgaabs.htm#sess8" NAME="sess8">
Applications in Image/Video Compression
</A></H2>
<I>Chair: Miriam Leeser, Northeastern University</I>
<DL>
<DT>
<A HREF="fpgaabs.htm#8_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/8_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Pipelined Architecture for Partitioned DWT Based Lossy Image
Compression using FPGA's [p. 201]
<DD><I>J. Ritter and P. Molitor (Martin-Luther-University Halle-Wittenberg)</I><P>
<DT>
<A HREF="fpgaabs.htm#8_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/8_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An FPGA-Based Video Compressor for H.263 Compatible Bit Streams [p. 207]
<DD><I>G. Lienhart, R. M�nner (University of Mannheim), R. Lay and K. H. Noffz (Silicon Software GmbH)</I><P>
<DT>
<A HREF="fpgaabs.htm#8_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/8_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
FPGA Implementation of a Novel, Fast Motion Estimation Algorithm
for Real-Time Video Compression [p. 213]
<DD><I>S. Ramachandran and S. Srinivasan (Indian Institute of Technology, Madras)</I><P>
</DL>
<HR>
<H2><A HREF="fpgaabs.htm#posabs" NAME="posabs">
Poster Paper
</A></H2>
<I></I>
(Alphabetically by Title)<P>
<DT>
<A HREF="fpgaabs.htm#pos1"><IMG SRC="../../../../../icons/absicon.gif"></A>
An Asynchronous Self-Routing Adaptive Reconfigurable FPGA [p. 223]
<DD><I>M. Ferranti and A. Lodi</I><P>
<DT>
<A HREF="fpgaabs.htm#pos2"><IMG SRC="../../../../../icons/absicon.gif"></A>
A Comparison of FPGA Implementations of Two�s Complement Bit-Level
and Word-Level Matrix Multipliers [p. 223]
<DD><I>Radhika S. Grover, Weijia Shang, and Qiang Li</I><P>
<DT>
<A HREF="fpgaabs.htm#pos3"><IMG SRC="../../../../../icons/absicon.gif"></A>
Corner Turning Interconnect for an FPGA: Motivation and Routing [p. 223]
<DD><I>Nicholas Weaver and John Wawrzynek</I><P>
<DT>
<A HREF="fpgaabs.htm#pos4"><IMG SRC="../../../../../icons/absicon.gif"></A>
Decoder-Driven Switching Matrices in Multicontext FPGAs:
Area, Routability and Speed [p. 224]
<DD><I>V. Baena-Lecuyer, M. A. Aguirre, A. Torralba, and L. G. Franquelo</I><P>
<DT>
<A HREF="fpgaabs.htm#pos5"><IMG SRC="../../../../../icons/absicon.gif"></A>
Design and Implementation of a Variable Length Packet Switch Board [p. 224]
<DD><I>Chan Kim, Ji-Myung Rho, Tae-Whan Yoo, and Jong-Hyun Lee</I><P>
<DT>
<A HREF="fpgaabs.htm#pos6"><IMG SRC="../../../../../icons/absicon.gif"></A>
Evaluation of Novel FPGA Features for Automotive Multimedia Applications [p. 224]
<DD><I>Karl G. Esser, Carsten Oetker, Karlheinz Weiss, and Wolfgang Rosenstiel
</I><P>
<DT>
<A HREF="fpgaabs.htm#pos7"><IMG SRC="../../../../../icons/absicon.gif"></A>
Fast Reconfigurable Multiplier for FPGA [p. 225]
<DD><I>S�bastien Favard and Mohamed Shawky</I><P>
<DT>
<A HREF="fpgaabs.htm#pos8"><IMG SRC="../../../../../icons/absicon.gif"></A>
Field Programmable Analog Array Modeling Approach For Fast Prototyping [p. 225]
<DD><I>S. Colancon, G. Cambon, L. Torres, and C. Dufaza</I><P>
<DT>
<A HREF="fpgaabs.htm#pos9"><IMG SRC="../../../../../icons/absicon.gif"></A>
An FPGA Architecture with Configurable Multiplier and Carry Units
for Improved Arithmetic Performance [p. 225]
<DD><I>Kamal Rajagopalan and Peter Sutton</I><P>
<DT>
<A HREF="fpgaabs.htm#pos10"><IMG SRC="../../../../../icons/absicon.gif"></A>
FPGA Hardware Synthesis from MATLAB Utilizing Optimized IP Cores [p. 226]
<DD><I>Malay Haldar, Anshuman Nayak, Alok Choudhary, and Prith Banerjee</I><P>
<DT>
<A HREF="fpgaabs.htm#pos11"><IMG SRC="../../../../../icons/absicon.gif"></A>
Implementation of a VME Bus to Internal Bus Bridge FPGA Core [p. 226]
<DD><I>Xavier Rev�s, Antoni Gelonch, J. L. Garcia, and Ferran Casadevall</I><P>
<DT>
<A HREF="fpgaabs.htm#pos12"><IMG SRC="../../../../../icons/absicon.gif"></A>
The Machine CEPRA-S Configured for Stream Processing [p. 226]
<DD><I>Rolf Hoffmann, Bernd Ulmann, Klaus-Peter V�lkmann, and Stefan Waldschmidt</I><P>
<DT>
<A HREF="fpgaabs.htm#pos13"><IMG SRC="../../../../../icons/absicon.gif"></A>
Motivation from a Full-Rate Specific Design to a DSP Core Approach
for All GSM Vocoders [p. 227]
<DD><I>Shervin Sheidaei, Hamid Noori, Ahmad Akbari, and Hosein Pedram</I><P>
<DT>
<A HREF="fpgaabs.htm#pos14"><IMG SRC="../../../../../icons/absicon.gif"></A>
Netlist Partitioning for Accelerated Verification Systems [p. 227]
<DD><I>Joachim Pistorius and Michel Minoux</I><P>
<DT>
<A HREF="fpgaabs.htm#pos15"><IMG SRC="../../../../../icons/absicon.gif"></A>
Proving Safety Properties of FPGAs [p. 227]
<DD><I>Adrian Hilton and Jon Hall</I><P>
<DT>
<A HREF="fpgaabs.htm#pos16"><IMG SRC="../../../../../icons/absicon.gif"></A>
PuMA++: A Fully Automatic Path from Specification to Multi-FPGA-Prototype [p. 228]
<DD><I>Klaus Harbich, Oliver Bringmann, and Erich Barke</I><P>
<DT>
<A HREF="fpgaabs.htm#pos17"><IMG SRC="../../../../../icons/absicon.gif"></A>
RCMAT: A Reconfigurable Coprocessor for Matrix Algorithms [p. 228]
<DD><I>A. Amira, A. Bouridane, and P. Milligan</I><P>
<DT>
<A HREF="fpgaabs.htm#pos18"><IMG SRC="../../../../../icons/absicon.gif"></A>
Reconfigurability in Embedded Microprocessors: A Prototyping Study [p. 228]
<DD><I>Sergej Sawitzki, Steffen K�hler, and Rainer G. Spallek</I><P>
<DT>
<A HREF="fpgaabs.htm#pos19"><IMG SRC="../../../../../icons/absicon.gif"></A>
Systems Prototyping Dedicated to Neural Network Real-Time Image Processing [p. 229]
<DD><I>
Rolf F. Molz, Paulo M. Engel, Fernando G. Moraes, Lionel Torres, and Michel
Robert
</I><P>
<DT>
<A HREF="fpgaabs.htm#pos20"><IMG SRC="../../../../../icons/absicon.gif"></A>
The Systolic Ring: A Reconfigurable Systolic Architecture [p. 229]
<DD><I>
Gille Sassatelli, G. Cambon, J�rome Galy, and Lionel Torres
</I><P>
<DT>
<A HREF="fpgaabs.htm#pos21"><IMG SRC="../../../../../icons/absicon.gif"></A>
Task Partitioning Between a General Purpose Microprocessor
and Reconfigurable Hardware [p. 229]
<DD><I>
Nitij Mangal, Puneet Gupta, and C. P. Ravikumar
</I><P>
<DT>
<A HREF="fpgaabs.htm#pos22"><IMG SRC="../../../../../icons/absicon.gif"></A>
Two-Dimensional 8x8 Fast Cosine Transform Parallel Processor [p. 230]
<DD><I>
Anatoly Melnyk, Yury Ermetov, and Bohdan Dunets
</I><P>
<DT>
<A HREF="fpgaabs.htm#pos23"><IMG SRC="../../../../../icons/absicon.gif"></A>
A Universal Fault-Tolerant Methodology in SRAM-Based FPGA Systems [p. 230]
<DD><I>
Yanmei Li, Dongmei Li, and Zhihua Wang
</I><P>
</DL>
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