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"; // As always, feel free to contact me with questions. // Eric Carter, ecarter@uci.edu ?> EECS 31/CSE 31/ICS 151 :: Daniel D. Gajski's Web Site

Welcome to the EECS 31/CSE 31/ICS 151 Course Web Site

EECS 31/CSE 31/ICS 151: Principles of Digital Design (Spring 2013)

ICS 151 1999 class pictureEECS 31/CSE 31/ICS 151 is the introductory course in digital design. First, students learn basic concepts of computer science and computer engineering such as binary number representation and arithmetic, Boolean algebra, finite-state-machine and instruction-set processors. They also learn basic logic and register-transfer components for design such as gates, flip flops, adders, multipliers, registers, memories and processors. Secondly, students learn the basics of design science. That is, how to convert design specifications into working implementations. They learn how to construct register-transfer components and how to optimize them for performance and cost. Furthermore, they learn how to design basic system components such as simple processors and custom hardware blocks. The course stresses the principles of design science and gives in each lecture clear and simple procedures on how to arrive at the best design from the given specification.

Additional Course Information

Course Title Principles of Digital Design
Instructor Daniel D. Gajski
Office Location 3207 Engineering Hall
Office Hours After class or by appointment
Lecture M, W, F, 9:00AM-9:50AM in SSPA 1100
TAs/Readers Quoc-Viet Dang (Email: qpdang@uci.edu)
Bryan Donyanavard (Email: bdonyana@uci.edu)
Pouria Khaliliadl (Email: pkhalili@uci.edu)
Yasaman Samei (Email: ysameisy@uci.edu)
TA Office Hours By appointment only for administrative issues
Discussion Section F, 10:00AM - 10:50AM in SSL 290
F, 11:00AM - 11:50AM in SSL 290
F, 12:00PM - 12:50PM in SSL 290
F, 1:00PM - 1:50PM in SSL 290
Final Exam Wednesday, June 12, 2013, 8:00-10:00AM, in SSPA 1100 or any proctoring facility
Midterms Friday, April 19, 2013, 9:00-9:50 AM, in SSPA 1100 or any proctoring facility
Friday, May 10, 2013, 9:00-9:50 AM, in SSPA 1100 or any proctoring facility
Primary Textbook Frank Vahid, Digital Design with RTL Design, VHDL, and Verilog, SECOND EDITION, John Wiley, 2011.
Useful References D. D. Gajski, Principles of Digital Design, Prentice Hall, 1997
Lab Take EECS 31L/ CSE 31L
Summer Session Summer session is 5 weeks with double load/week
On-Line On-line course exams can be taken on campus or at any proctoring facility (NCTA listing for proctoring facilities)
Calendar Tentative lecture, homework, and exam schedule can be found here: Digital Design 101 Google Calendar

Intro

Boolean Algebra

Gates

Gate-Optimization

Combinatorial-RTL-Components

Sequential-Design

Finite-state-machine

Storage RTL Components

C-to-RTL

Processor/IP Design