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Much effort in RTL design has been devoted to developing push-button types of tools. However, given the highly complex nature of RTL design, interactive design space exploration with assistance of tools and algorithms can be more effective. In this report, we propose an interactive RTL design environment, targeting a generic RTL processor architecture including pipelining, multicycling and chaining. Tasks in the RTL design process include clock definition, component allocation, scheduling, binding, and validation. In our interactive design environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. We also provide a simultaneous scheduling and binding algorithm to automate RTL synthesis process. In the end, we present a set of experimental results that demonstrates the benefits of the proposed approach.

This report presents methodology and algorithms for generating bus functional models from transaction level models in system level design. Transaction level models are often used by designers for prototyping the bus functional architecture of the system. Being at a higher level of abstraction gives transaction level models the unique advantage of high simulation speed. This means that the designer can explore several bus functional architectures before choosing the optimal one. However, the process of converting a transaction level model to a bus functional model is not trivial. A manual conversion would not only be time consuming but also error prone. A bus functional model should also accurately represent the corresponding transaction level model. We present algorithms for automating this refinement process. Experimantal results presented using a tool based on these algorithms show their usefulness and feasibility.

The continuous increase in size and complexity of System-on-Chip designs has introduced new modeling and verification challenges. The system designs of today need modeling at higher levels of abstraction such as transaction level. On the verification front, techniques like assertion based verification are being used to complement traditional simulation and debugging of designs. Formal methods like logical equivalence checking are becoming increasingly relevant for minimizing or even eliminating the need for costly gate-level simulations. Property checking techniques like model checking and theorem proving are being employed in high-end processor and system design.

In this talk, we will present an overview on the role of modeling and verification in the complete design flow from system level to gates. We will discuss different models and the verification techniques that apply best for validating them.

As we are entering the network-on-chip era and system communication is becoming a dominating factor, communication abstraction and synthesis are integral to defining system design flows and methodologies. The key to the success of any approach, however, are well-defined abstraction levels and models, which enable design automation for synthesis and verification to achieve the required productivity gains. In this report, we define a flow of system communication abstraction layers and corresponding design models that supports design automation for successive, step-wise refinement of communication from abstract application transactions down to a bus-functional implementation. We applied the flow to the example of a mobile baseband chip platform. Results show the trade-offs between accuracy and complexity of different transaction levels in the flow. Furthermore, the experiments demonstrate the effectiveness and feasibility of an automated flow.

This paper presents a formal approach to correctly generate an architecture level model of a system from its specification model. We define the notion of equivalence of models based on their execution semantics. A formalism is then presented, which can be used to model systems and perform correct transformations on them. Architecture refinement is described, as a sequence of such transformations on the specification model, that results in an equivalent architecture model. This method of deriving one model from another through well defined rules can alleviate the problem of validating every model at different abstraction levels in system design.

With complexities of Systems-on-Chip rising almost daily, the design community has been searching for new methodology that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear how many of these building blocks we need and what these basic blocks should be. Obviously, the necessary building blocks are processors and memories. One interesting question is: Are they sufficient? The other interesting question is: How many types of processors and memories we really need? In this report we try to answer both of these questions and argue that the No-instruction-set computer (NISC) is a single, necessary and sufficient processor component for design of any digital system.

Many recently proposed system-level design methodologies share the characteristic that the design flow starts from a golden, executable specification model. The specification model is captured by the designer and describes the desired system behavior in a purely functional way. As the starting point for the system-level design process, it will later be gradually refined through a series of interactive and automated steps down to an actual implementation. Therefore, having a clear and unambigious input model as defined by this manual is crucial for effective design space exploration.

In this report, we will describe and define a system specification style guide using the SpecC language and the design flow in the System-on-Chip Design Environment (SCE) as an example. Following some general guidelines for developing efficient specification models, detailed rules that define the specification modeling style are given. For the example of SCE used in this report, specification models are written in version 2.0 of the SpecC language. On top of the basic SpecC syntax and semantics, the modeling rules impose additional restrictions for a proper and valid specification model. Finally, steps required to convert an existing C description into a specification model are outlined and some conversion examples are given.

We present a methodology and style guidelines for automatic translation from a given design specification in raw C code to SpecC code. Traditional conversion from C to SpecC relies on manual refinement which is painfully time consuming and error prone. The automation of the refinement process provides a useful tool to reduce the time spent in conversion of C to SpecC so that the system designer can spend more time with design decisions based on exploration with SpecC code.

Rasing the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impact on system performance, it is much desired that the designer can select the right scheduling algorithm at high abstraction levels so as to save him from the error-prone and time consuming task of tuning code delays or task priority assignments at the final stage of system design. In this paper we tackle this problem by introducing a RTOS model and an approach to refine any unscheduled transaction level model (TLM) to a TLM with RTOS scheduling support. The automation of the RTOS scheduling refinement process provides a useful tool to the system designer to quickly evaluate different dynamic scheduling algorithms and make the optimal choice at the early stage of system design. Experiments with the tool on a system design example shows the usefulness of our approach.

In course of system-level design, designers need an efficient system level design language (SLDL), which can serve as the design vehicle. The complexity of the design process at this level is determined upto an extent, by the semantics and syntax definition of the SLDL being used. This report first analyzes the system-level design flow in order to establish the requirements on an SLDL. It then compares SpecC and SystemC, the two popular SLDLs, in terms of the extent they meet these requirements. Finally, it provides the essential modeling guidelines for both the SpecC and SystemC users for the cases where the constructs or the features of the respective languages give rise to an ambiguous design.

Recently, the transaction-level modeling is widely referred to in system level design literature. However, the transaction-level models (TLMs) are not well defined and the usages of TLM in the existing design approaches, namely system synthesis, platform-based design, and component-based design, are not systematically developed. In order to efficiently use TLMs in above design approaches, this report defines four transaction level abstraction models. The defined TLMs slice the entire design process into several small design tasks. Each task targets at a specific design objective and the result of a task can be validated by simulating the corresponding TLM. Designers can extract the characteristics of the design from lower-level TLMs and annotate them to the higher-level TLMs, such that designers can accurately make design decision at early stages. Using defined TLMs as standard models, designers can reuse/exchange the pre-defined TLMs and implement the cross-approach design.

This report presents a methodology towards a complete software implementation of G.729 Annexe E on ARM926EJ-S processor running at 200 MHz clock speed. The methodology spans both, target independent as well as target dependent optimizations. The main focus is towards code speed up to reduce the per frame execution time as much below the 10 ms constraint as possible. Although no constraint is given for code size, the outcome of the optimization process has so far resulted in an overall reduction of the code size. The code was also run on an Aptix FPGA board to calibrate the ARMulator (ARM instruction set simulator). Although the optimizations presented here, were performed and analyzed on the G.729E algorithm, they can be used on any similar DSP code for speed up.

This paper presents a methodology and algorithms for automatic communication refinement. The communication refinement task in system-level synthesis transforms abstract data-transfer between components to its actual bus level implementation. The input model of the communication refinement is a set of concurrently executing components, communicating with each other through abstract communication channels. The refined model reflects the actual communication architecture. Choosing a good communication architecture in system level designs requires sufficient exploration through evaluation of various architectures. However, this would not be possible with manually refining the system model for each communication architecture. For one, manual refinement is tedious and error-prone. Secondly, it wastes substantial amount of precious designer time. We solve this problem with automatic model refinement. We also present a set of experimental results to demonstrate how the proposed approach works on a typical system level design.

This report presents a formal approach to verify models in a system level design environment. It is a first in series of reports that demonstrate how we use this formal approach to refine a given specification down to its cycle-accurate implementation. We formally define models and develop theorems and proofs to show that our well defined refinement algorithms produce functionally equivalent models. In this report, we specifically look at generation of an architecture level model by refinement of a specification model. The refinement process follows a well defined system level partitioning algorithm. We prove that executing the individual steps of the refinement algorithm, in the predefined order, leads to an equivalent model.

This report proposes a design flow and algorithms to implement the channel mapping, which generates interconnection topology of the system architecture, selects bus protocols, maps the communication channels among PEs to the generated buses, and configures bus parameters. Unlike previous work, the proposed design flow and algorithms are tailored for complex systems which contain hundreds of PEs with incompatible communication protocols. We have applied the proposed approach on the vocoder project and have approved the approach's correctness.